A multi-mode IFFT/FFT processor for IEEE 802.11ac: design and implementation

In this paper, we present 64/128/256/512 point inverse fast Fourier transform (IFFT)/FFT processor for single-user and multi-user multiple-input multipleoutput orthogonal frequency-division multiplexing based IEEE 802.11ac wireless local area network transceiver. The multi-mode processor is developed by an eight-parallel mixed-radix architecture to efficiently produce full reconfigurability for all multi-user combinations. The proposed design not only supports the operation of IFFT/FFT for 1-8 different data streams operated by different users in case of downlink transmission, but also it provides different throughput rates to meet IEEE 802.11ac requirements at the minimum possible clock frequency. Moreover, less power is needed in our design compared with traditional software approach. The design is carefully optimized to operate by the minimum wordlengths that full fill the performance and complexity specifications. The processor is designed and implemented on Xilinx Vertix-5 field programmable gate array technology. Although the maximum clock frequency is 377.84MHz, the processor is clocked by the operating sampling rate to further reduce the power consumption. At the operation clock rate of 160 MHz, our proposed processor can calculate 512-point FFT with up to eight independent data sequences within 3.2μsec meeting IEEE 802.11ac standard requirements.